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lyt4211-4218/4311-4318 lytswitch high power led driver ic family www.powerint.com february 2013 single-stage accurate primary-side constant current (cc) controller with pfc for low-line applications, triac dimming and non-dimming options ? product highlights ? better than 5% cc regulation ? triac dimmable to less than 5% output ? fast start-up ? <250 ms at full brightness ? <1s at 10% brightness ? high power factor >0.9 ? easily meets en61000-3-2 ? less than 10% thd in optimized designs ? up to 92% effcient ? 132 khz switching frequency for small magnetics high performance, combined driver, controller, switch the lytswitch family enables off-line led drivers with high power factor which easily meet international requirements for thd and harmonics. output current is tightly regulated with better than 5% cc tolerance 1 . effciency of up to 92% is easily achieved in typical applications. supports a wide selection of triac dimmers the lytswitch family provides excellent turn-on characteristics for leading-edge and trailing-edge triac dimming applications. this results in drivers with a wide dimming range and fast start-up, even when turning-on from a low conduction angle. large dimming ratio and low pop-on current. low solution cost and long lifetime lytswitch ics are highly integrated and employ a primary-side control technique that eliminates the optoisolator and reduces component count. this allows the use of low-cost single-sided printed circuit boards. combining pfc and cc functions into a single-stage also helps reduce cost and increase effciency. the 132 khz switching frequency permits the use of small, low-cost magnetics. led drivers using the lytswitch family do not use primary-side aluminum electrolytic bulk capacitors. this means greatly extended driver lifetime, especially in bulb and other high temperature applications. figure 1. typical schematic. control part number input voltage range triac dimmable ly t4211-ly t4218 85-132 vac no ly t4311-ly t4318 85-132 vac yes output power table 1,2 product 6 minimum output power 3 maximum output power 4 lyt4 x 11e/l 5 2.5 w 12 w lyt4x12e/l 2.5 w 15 w lyt4x13e/l 3.8 w 18 w lyt4x14e/l 4.5 w 22 w lyt4x15e/l 5.5 w 25 w lyt4x16e/l 6.8 w 35 w lyt4x17e/l 8.0 w 50 w lyt4x18e/l 18 w 78 w table 1. output power table. notes : 1. performance for typical design. see applications section. 2. continuous power in an open-frame design with adequate heat sinking; device local ambient of 70 c. power level calculated assuming a typical led string voltage and effciency >80%. 3. minimum output power requires c bp = 47 f. 4. maximum output power requires c bp = 4.7 f. 5. lyt4311 c bp = 47 f, lyt4211 c bp = 4.7 f. 6. package: esip-7c, esip-7f (see figure 2). figure 2. package options. esip-7f (l package) esip-7c (e package) optimized for different applications and power levels
rev. b 02/13 2 lyt4211-4218/4311-4318 www.powerint.com figure 3d. typical buck-boost schematic. figure 3c. typical tapped buck schematic. figure 3b. typical buck schematic. figure 3a. typical isolated flyback schematic. table 2. performance of different topologies in a typical non-dimmable 10 w low-line design. control topology isolation effciency cost thd output voltage isolated flyback yes 88% high best any buck no 92% low good limited tapped buck no 89% middle best any buck-boost no 90% low best high-voltage pi-6841-081512 d s bp v fb r control ac in lytswitch pi-6842-081512 d s bp control ac in v fb r lytswitch typical circuit schematic key features flyback benefts ? provides isolated output ? supports widest range of output voltages ? very good thd performance limitations ? flyback transformer ? overall effciency reduced by parasitic capacitance and inductance in the transformer ? larger pcb area to meet isolation requirements ? requires additional components (primary clamp and bias) ? higher rms switch and winding currents increases losses and lowers effciency buck benefts ? highest effciency ? lowest component count C small size ? simple low-cost power inductor ? low drain source voltage stress ? best emi/lowest component count for flter limitations ? single input line voltage range ? output voltage <0.6 v in(ac) 1.41 ? output voltage for low thd designs ? non-isolated tapped buck benefts ? ideal for low output voltage designs (<20 v) ? high effciency ? low component count ? simple low-cost tapped inductor limitations ? designs best suited for single input line voltage ? requires additional components (primary clamp) ? non-isolated buck-boost benefts ? ideal for non-isolated high output voltage designs ? high effciency ? low component count ? simple common low-cost power inductor can be used ? lowest thd limitations ? maximum v out is limited by mosfet breakdown voltage ? single input line voltage range ? non-isolated pi-6859-081512 d s bp v fb r control ac in lytswitch
rev. b 02/13 3 lyt4211-4218/4311-4318 www.powerint.com figure 5. pin confguration. pin functional description drain (d) pin: this pin is the power fet drain connection. it also provides internal operating current for both start-up and steady-state operation. source (s) pin: this pin is the power fet source connection. it is also the ground reference for the bypass, feedback, reference and voltage monitor pins. bypass (bp) pin: this is the connection point for an external bypass capacitor for the internally generated 5.9 v supply. this pin also provides output power selection through choice of the bypass pin capacitor value. feedback (fb) pin: the feedback pin is used for output voltage feedback. the current into the feedback pin is directly proportional to the output voltage. the feedback pin also includes circuitry to protect against open load and overload output conditions. reference (r) pin: this pin is connected to an external precision resistor and is used to confgure for dimming (lyt4311-4318) and non-triac dimming (lyt4211-4218) modes of operation. voltage monitor (v) pin: this pin interfaces with an external input line peak detector, consisting of a rectifer, flter capacitor and resistors. the applied current is used to control stop logic for overvoltage (ov), provide feed-forward to control the output current and the remote on/off function. pi-6843-071112 i lim drain (d) source (s) bypass (bp) voltage monitor (v) feedback (fb) reference (r) i lim v sense m i i s 5.9 v 5.0 v bypass pin undervoltage fault present gate driver sensefet ocp current limit comparator 1 v 6.4 v fb off fb off i fb i v dc max dc max comparator 5.9 v regulator soft-start timer jitter clock oscillator auto-restart counter bypass capacitor select feedback sense pfc/cc control line sense hysteretic thermal shutdown + - + - + - 3-v t v bg ov reference block leb m i v bg stop logic pi-5432-082411 exposed pad (backside) internally connected to source pin (see esip-7c package drawing) 1 r 2 v 3 fb 4 bp 5 s 7 d e package (esip-7c) (top view) lead bend outward from drawing (refer to esip-7f package outline drawing) exposed pad (backside) internally connected to source pin 7 d 5 s 4 bp 3 fb 2 v 1 r l package (esip-7f) figure 4. functional block diagram.
rev. b 02/13 4 lyt4211-4218/4311-4318 www.powerint.com functional description a lytswitch device monolithically combines a controller and high-voltage power fet into one package. the controller provides both high power factor and constant current output in a single-stage. the lytswitch controller consists of an oscillator, feedback (sense and logic) circuit, 5.9 v regulator, hysteretic over-temperature protection, frequency jittering, cycle-by-cycle current limit, auto-restart, inductance correction, power factor and constant current control. feedback pin current control characteristics the fgure shown below illustrates the operating boundaries of the feedback pin current. above i fb(skip) switching is disabled and below i fb(ar) the device enters into auto-restart. figure 6. feedback pin current characteristic. the feedback pin current is also used to clamp the maximum duty cycle to limit the available output power for overload and open-loop conditions. this duty cycle reduction characteristic also promotes a monotonic output current start-up characteristic and helps preventing over-shoot. reference pin the reference pin is tied to ground (source) via an external resistor. the value selected sets the internal references, determining the operating mode for dimming (lyt4311-4318) and non-dimming (lyt4211-4218) operation and the line overvoltage thresholds of the voltage monitor pin. for non-dimming or pwm dimming applications with lyt4211-4218, the external resistor should be a 24.9 k w 1%. for phase angle ac dimming with lyt4311-4318, the external resistor should be a 49.9 k w 1%. one percent resistors are recommended as the resistor tolerance directly affects the output tolerance. other resistor values should not be used. bypass pin capacitor power gain selection lytswitch devices have the capability to tailor the internal gain to either full or a reduced output power setting. this allows selection of a larger device to minimize dissipation for both thermal and effciency reasons. the power gain is selected with the value of the bypass pin capacitor. the full power setting is selected with a 4.7 f capacitor and the reduced power setting (for higher effciency) is selected with a 47 f capacitor. the bypass pin capacitor sets both the internal power gain as well as the over-current protection (ocp) threshold. unlike the larger devices, the lyt4x11 power gain is not programmable. use a 47 f capacitor for the lyt4x11. switching frequency the switching frequency is 132 khz during normal operation. to further reduce the emi level, the switching frequency is jittered (frequency modulated) by approximately 2.6 khz. during start-up the frequency is 66 khz to reduce start-up time when the ac input is phase angle dimmed. jitter is disabled in deep dimming. soft-start the controller includes a soft-start timing feature which inhibits the auto-restart protection feature for the soft-start period (t soft ) to distinguish start-up into a fault (short-circuit) from a large output capacitor. at start-up the lytswitch clamps the maximum duty cycle to reduce the output power. the total soft-start period is t soft . remote on/off and ecosmart ? the voltage monitor pin has a 1 v threshold comparator connected at its input. this voltage threshold is used for remote on/off control. when a signal is received at the voltage monitor pin to disable the output (voltage monitor pin tied to ground through an optocoupler photo- transistor) the lytswitch will complete its current switching cycle before the internal power fet is forced off. the remote on/off feature can also be used as an eco-mode or power switch to turn off the lytswitch and keep it in a very low power consumption state for indefnite long periods. when the lytswitch is remotely turned on after entering this mode, it will initiate a normal start-up sequence with soft-start the next time the bypass pin reaches 5.9 v. in the worst case, the delay from remote on to start-up can be equal to the full discharge/charge cycle time of the bypass pin. this reduced consumption remote off mode can eliminate expensive and unreliable in-line mechanical switches. i fb(ar) i fb(dcmaxr) dc10 dc max i fb(skip) i fb pi-5433-060410 skip-cycle cc control region soft-start and cc fold-back region auto-restart maximum duty cycle
rev. b 02/13 5 lyt4211-4218/4311-4318 www.powerint.com figure 7. remote on/off voltage monitor pin control. 5.9 v regulator/shunt voltage clamp the internal 5.9 v regulator charges the bypass capacitor connected to the bypass pin to 5.9 v by drawing a current from the voltage on the drain pin whenever the power fet is off. the bypass pin is the internal supply voltage node. when the power fet is on, the device operates from the energy stored in the bypass capacitor. extremely low power consumption of the internal circuitry allows lytswitch to operate continuously from current it takes from the drain pin. a bypass capacitor value of 47 or 4.7 f is suffcient for both high frequency decoupling and energy storage. in addition, there is a 6.4 v shunt regulator clamping the bypass pin at 6.4 v when current is provided to the bypass pin through an external resistor. this facilitates powering of lytswitch externally through a bias winding to increase operating effciency. it is recommended that the bypass pin is supplied current from the bias winding for normal operation. auto-restart in the event of an open-loop fault (open feedback pin resistor or broken path to feedback winding), output short-circuits or an overload condition the controller enters into the auto-restart mode. the controller annunciates both short-circuit and open-loop conditions once the feedback pin current falls below the i fb(ar) threshold after the soft-start period. to minimize the power dissipation under this fault condition the shutdown/ auto-restart circuit turns the power supply on (same as the soft-start period) and off at an auto-restart duty cycle of typically dc ar for as long as the fault condition persists. if the fault is removed during the auto-restart off-time, the power supply will remain in auto-restart until the full off-time count is completed. special consideration must be made to appropriately size the output capacitor to ensure that after the soft-start period (t soft ) the feedback pin current is above the i fb(ar) threshold to ensure successful power-supply start-up. after the soft-start time period, auto-restart is activated only when the feedback pin current falls below i fb(ar) . over-current protection the current limit circuit senses the current in the power fet. when this current exceeds the internal threshold (i limit ), the power fet is turned off for the remainder of that cycle. a leading edge blanking circuit inhibits the current limit comparator for a short time (t leb ) after the power fet is turned on. this leading edge blanking time has been set so that current spikes caused by capacitance and rectifer reverse recovery will not cause premature termination of the power fet conduction. line overvoltage protection this device includes overvoltage detection to limit the maximum operating voltage detected through the voltage monitor pin. an external peak detector consisting of a diode and capacitor is required to provide input line peak voltage to the voltage monitor pin through a resistor. the resistor sets line overvoltage (ov) shutdown threshold which, once exceeded, forces the lytswitch to stop switching. once the line voltage returns to normal, the device resumes normal operation. a small amount of hysteresis is provided on the ov threshold to prevent noise-generated toggling. when the power fet is off, the rectifed dc high voltage surge capability is increased to the voltage rating of the power fet (670 v), due to the absence of the refected voltage and leakage spikes on the drain. hysteretic thermal shutdown the thermal shutdown circuitry senses the controller die temperature. the threshold is set at 142 c typical with a 75 c hysteresis. when the die temperature rises above this threshold (142 c) the power fet is disabled and remains disabled until the die temperature falls by 75 c, at which point the power fet is re-enabled. safe operating area (soa) protection the device also features a safe operating area (soa) protection mode which disables fet switching for 40 cycles in the event the peak switch current reaches the i limit threshold and the switch on-time is less than t on(soa) . this protection mode protects the device under short-circuited led conditions and at start-up during the soft-start period when auto-restart protection is inhibited. the soa protection mode remains active in normal operation. pi-5435-052510 d s bp v r fb control
rev. b 02/13 6 lyt4211-4218/4311-4318 www.powerint.com application example 25 w triac dimmable high power factor led driver design example (der-350) the circuit schematic in figure 8 shows a triac dimmable high power factor led driver based on lyt4317e from the lytswitch family of devices. the design is confgurable for non-dimmable only applications by simple component value changes. it was optimized to drive an led string at a voltage of 36 v with a constant current of 0.7 a ideal for lumens par lamp retro-ft applications. the design operates over an input voltage range of 90 vac to 132 vac. the key goals of this design were compatibility with standard leading edge triac ac dimmers, very wide dimming range (1000:1, 700 ma:0.7 ma), high effciency (>85%) and high power factor (>0.9). the design is fully protected from faults such as no-load (open load), overvoltage and output short-circuit or overload conditions and over temperature. circuit description the lytswitch device (u1- lyt4317e) integrates the power fet, controller and start-up functions into a single package reducing the component count versus typical implementations. confgured as part of an isolated continuous conduction mode fyback converter, u1 provides high power factor via its internal control algorithm together with the small input capacitance of the design. continuous conduction mode operation results in reduced primary peak and rms current. this both reduces emi noise, allowing simpler, smaller emi fltering components and improves effciency. output current regulation is maintained without the need for secondary-side sensing which eliminates current sense resistors and improves effciency. input stage fuse f1 provides protection from component failures while rv1 provides a clamp during differential line surges, keeping the peak drain voltage of u1 below the 725 v rating of the internal power fet. bridge rectifer br1 rectifes the ac line voltage. emi fltering is provided by l1-l3, c1, c4, r2, r24 and r25 together with the safety rated y class capacitor (cy1) that bridges the safety isolation barrier between primary and secondary. resistor r2, r24 and r25 act to damp any resonances formed between l1, l2, l3, c1 and the ac line impedance. a small bulk capacitor (c4) is required to provide a low impedance source for the primary switching current. the maximum value of c2 and c4 is limited in order to maintain a power factor of greater than 0.9. lytswitch primary to provide peak line voltage information to u1 the incoming rectifed ac peak charges c6 via d2. this is then fed into the voltage monitor pin of u1 as a current via r10. this sensed current is also used by the device to set the line input overvoltage protection threshold. resistor r9 provides a discharge path for c6 with a time constant much longer than that of the rectifed ac to prevent generation of line frequency ripple. the voltage monitor pin current and the feedback pin current are used internally to control the average output led current. for triac phase-dimming applications a 49.9 k w resistor (r14) is used on the reference pin and 2 m w (r10) on the voltage monitor pin to provide a linear relationship between input voltage and the output current and maximizing the dimming range. diode d3, r15 and c7 clamp the drain voltage to a safe level due to the effects of leakage inductance. diode d4 is necessary to prevent reverse current from fowing through u1 for the period of the rectifed ac input voltage that the voltage across c4 falls to below the refected output voltage (v or ). r6 360 k? pi-6875-101812 d s bp v r fb control fl1 t1 rm8 12 1 fl2 10 11 r10 2 m? 1% r15 200 k? r9 510 k? 1/8 w r24 47 k? 1/8 w r1 510 1/2 w r25 47 k? 1/8 w r2 47 k? 1/8 w l1 1 mh l2 1 mh r14 49.9 k? 1% 1/16 w r18 165 k? 1% 1/16 w r23 20 k? 36 v, 700 ma 90 - 132 vac rtn l n r19 20 k? 1/8 w c5 100 nf 50 v r26 30 ? r20 39 ? 1/8 w r17 3 k? 1/10 w r27 10 ? 1/10 w d2 dflu1400 c7 2.2 nf 630 v d3 us1j d5 bav16 vr4 mazs3300ml 33 v q2 mmbt3904 d8 bav21 q1 x0202ma2bl2 d6 bav21 d7 byw29-200 d4 us1d r22 1 k? 1/10 w br1 mb6s 600 v rv1 140 vac f1 5 a c11 330 f 63 v c13 100 pf 200 v cy1 470 pf 250 vac c12 330 f 63 v c8 47 f 16 v c15 100 nf 50 v c14 10 nf 50 v c9 56 f 50 v lytswitch u1 lyt4317e c6 2.2 f 250 v c1 220 nf 250 v c4 100 nf 250 v l3 5 mh r8 100 ? 1 w c3 470 nf 50 v c2 100 nf 250 v d9 dflu1400-7 figure 8. der-350 schematic of an isolated, triac dimmable, high power factor, 90-132 vac, 25 w / 36 v / 700 ma led driver.
rev. b 02/13 7 lyt4211-4218/4311-4318 www.powerint.com diode d6, c5, c9, r19 and r20 create the primary bias supply from an auxiliary winding on the transformer. capacitor c8 provides local decoupling for the bypass pin of u1 which is the supply pin for the internal controller. during start-up c8 is charged to ~6 v from an internal high-voltage current source tied to the device drain pin. this allows the part to start switching at which point the operating supply current is provided from the bias supply via r17. capacitor c8 also selects the output power mode (47 f for reduced power was selected to reduce dissipation in u1 and increase effciency for this design). feedback the bias winding voltage is proportional to the output voltage (set by the turns ratio between the bias and secondary windings). this allows the output voltage to be monitored without secondary-side feedback components. resistor r18 converts the bias voltage into a current which is fed into the feedback pin of u1. the internal engine within u1 combines the feedback pin current, the voltage monitor pin current and drain current information to provide a constant output current over a 1.5:1 output voltage variation (led string voltage variation of 25%) at a fxed line input voltage. to limit the output voltage at no-load an output overvoltage protection circuit is set by d8, c15, r22, vr4, r27, c14 and q2. should the output load be disconnected then the bias voltage will increase until vr4 conducts, turning on q2 and reducing the current into the feedback pin. when this current drops below 10 a the part enters auto-restart and switching is disabled for 300 ms allowing time for the output and bias voltages to fall. output rectifcation the transformer secondary winding is rectifed by d7 and fltered by c11 and c12. an ultrafast to-220 diode was selected for effciency and the combined value of c11 and c12 were selected to give peak-to-peak led ripple current equal to 30% of the mean value. for designs where lower ripple is desirable the output capacitance value can be increased. a small pre-load is provided by r23 which discharges residual charge in output capacitors when turned off. triac phase dimming control compatibility the requirement to provide output dimming with low-cost, triac-based, leading edge phase dimmers introduces a number of trade-offs in the design. due to the much lower power consumed by led based lighting the current drawn by the overall lamp is below the holding current of the triac within the dimmer. this can cause undesirable behaviors such as limited dimming range and/or fickering as the triac fres inconsistently. the relatively large impedance the led lamp presents to the line allows signifcant ringing to occur due to the inrush current charging the input capacitance when the triac turns on. this too can cause similar undesirable behavior as the ringing may cause the triac current to fall to zero and turn off. to overcome these issues simple two circuits, the scr active damper and r-c passive bleeder, are incorporated. the drawback of these circuits is increased dissipation and therefore reduced effciency of the supply. for non-dimming applications these components can simply be omitted. the scr active damper consists of components r6, c3, and q1 in conjunction with r8. this circuit limits the inrush current that fows to charge c4 when the triac turns on by placing r8 in series for the frst ~1 ms of the triac conduction. after approximately 1 ms, q1 turns on and bypasses r8. this keeps the power dissipation on r8 low and allows a larger value during current limiting. resistor r6 and c3 provide the delay on q1 turn on after the triac conducts. diode d9 blocks the charge in capacitor c4 from fowing back after the triac turns on which helps in dimming compatibility especially with high power dimmers. the passive bleeder circuit is comprised of r1 and c1. this helps keep the input current above the triac holding current while the input current corresponding to the effective driver resistance increases during each ac half-cycle.
rev. b 02/13 8 lyt4211-4218/4311-4318 www.powerint.com modifed der-350 25 w high power factor led driver for non-dimmable and enhanced line regulation the circuit schematic in figure 9 shows a high power factor led driver based on a lyt4317 from the lytswitch family of devices. it was optimized to drive an led string at a voltage of 36 v with a constant current of 0.7 a, ideal for high lumen par lamp retro-ft applications. the design operates over the low-line input voltage range of 90 vac to 132 vac and is non-dimming application. a non-dimming application has tighter output current variation with changes in the line voltage than a dimming application. its key to note that, although not specifed for dimming, no circuit damage will result if the end user does operate the design with a phase controlled dimmer. modifcation for non-dimmable confguration the design is confgurable for non-dimmable application by simply removing the component for scr active damper (r6, r8, c3, and q1), blocking diode d9 and r-c bleeder (r1, c1) changes and replacing the reference resistor r14 with 24.9 k w . (see figure 9) key application considerations power table the data sheet power table (table 1) represents the minimum and maximum practical continuous output power based on the following conditions: ? effciency of 80% ? device local ambient of 70 c ? suffcient heat sinking to keep the device temperature below 100 c ? for minimum output power column ? refected output voltage (v or ) of 120 v ? feedback pin current of 135 a ? bypass pin capacitor value of 47 f ? for maximum output power column ? refected output voltage (v or ) of 65 v ? feedback pin current of 165 a ? bypass pin capacitor value of 4.7 f (lyt4x11 = 4.7 f) note that input line voltages above 85 vac do not change the power delivery capability of lytswitch devices. device selection select the device size by comparing the required output power to the values in table 1. for thermally challenging designs, e.g., incandescent lamp replacement, where either the ambient temperature local to the lytswitch device is high and/or there is minimal space for heat sinking use the minimum output power column. this is selected by using a 47 f bypass pin capacitor and results in a lower device current limit and therefore lower conduction losses. for open frame design or designs where space is available for heat sinking then refer to the maximum output power column. this is selected by using a 4.7 f bypass pin capacitor for all but the lyt4x11 which has only one power setting. in all cases in order to obtain the best output current tolerance maintain the device temperature below 100 c maximum input capacitance to achieve high power factor, the capacitance used in both the emi flter and for decoupling the rectifed ac (bulk capacitor) must be limited in value. the maximum value is a function of the output power of the design and reduces as the output power reduces. for the majority of designs limit the total capacitance to less than 200 nf with a bulk capacitor value of 100 nf. film capacitors are recommended compared to ceramic types as they minimize audible noise with operating with leading edge phase dimmers. start with a value of 10 nf for the capacitance in the emi flter and increase in value until there is suffcient emi margin. pi-6875a-101512 d s bp v r fb control fl1 t1 rm8 12 1 fl2 10 11 r10 2 m? 1% r15 200 k? r9 510 k? 1/8 w r24 47 k? 1/8 w r25 47 k? 1/8 w r2 47 k? 1/8 w l1 1 mh l2 1 mh r14 24.9 k? 1% 1/16 w r18 165 k? 1% 1/16 w r23 20 k? 36 v, 700 ma 90 - 132 vac rtn l n r19 20 k? 1/8 w c5 100 nf 50 v r26 30 ? r20 39 ? 1/8 w r17 3 k? 1/10 w r27 10 ? 1/10 w d2 dflu1400 c7 2.2 nf 630 v d3 us1j d5 bav16 vr4 mazs3300ml 33 v q2 mmbt3904 d8 bav21 d6 bav21 d7 byw29-200 d4 us1d r22 1 k? 1/10 w br1 mb6s 600 v rv1 140 vac f1 5 a c11 330 f 63 v c13 100 pf 200 v cy1 470 pf 250 vac c12 330 f 63 v c8 47 f 16 v c15 100 nf 50 v c14 10 nf 50 v c9 56 f 50 v lytswitch u1 lyt4317e c6 2.2 f 250 v c4 100 nf 250 v l3 5 mh c2 100 nf 250 v figure 9. modifed schematic of rd-350 for non-dimmable, isolated, high power factor, 90-132 vac, 25 w / 36 v led driver.
rev. b 02/13 9 lyt4211-4218/4311-4318 www.powerint.com reference pin resistance value selection the lytswitch family contains phase dimming devices, lyt4311-4318, and non-dimming devices, lyt4211-4218. the non-dimmable devices use a 24.9 k w 1% reference pin resistor for best output current tolerance (over ac input voltage changes). the dimmable devices (i.e. lyt4311-4318) use 49.9 k w 1% to achieve the widest dimming range. voltage monitor pin resistance network selection for widest ac phase angle dimming range with lyt4311-4318, use a 2 m w (1.7 m w for 100 vac (japan)) resistor connected to the line voltage peak detector circuit. make sure that the resistors voltage rating is suffcient for the peak line voltage. if necessary use multiple series connected resistors. primary clamp and output refected voltage v or a primary clamp is necessary to limit the peak drain to source voltage. a zener clamp requires the fewest components and board space and gives the highest effciency. rcd clamps are also acceptable however the peak drain voltage should be carefully verifed during start-up and output short-circuits as the clamping voltage varies with signifcantly with the peak drain current. for the highest effciency, the clamping voltage should be selected to be at least 1.5 times the output refected voltage, v or , as this keeps the leakage spike conduction time short. this will ensure effcient operation of the clamp circuit and will also keep the maximum drain voltage below the rated breakdown voltage of the fet. an rcd (or rcdz) clamp provides tighter clamp voltage tolerance than a zener clamp. the rcd clamp is more cost effective than the zener clamp but requires more careful design to ensure that the maximum drain voltage does not exceed the power fet breakdown voltage. these v or limits are based on the bv dss rating of the internal fet, a v or of 60 v to 100 v is typical for most designs, giving the best pfc and regulation performance. series drain diode an ultrafast or schottky diode in series with the drain is necessary to prevent reverse current fowing through the device. the voltage rating must exceed the output refected voltage, v or . the current rating should exceed two times the average primary current and have a peak rating equal to the maximum drain current of the selected lytswitch device. line voltage peak detector circuit lytswitch devices use the peak line voltage to regulate the power delivery to the output. a capacitor value of 1 f to 4.7 f is recommended to minimize line ripple and give the highest power factor (>0.9), smaller values are acceptable but result in lower pf and higher line current distortion. operation with phase controlled dimmers dimmer switches control incandescent lamp brightness by not conducting (blanking) for a portion of the ac voltage sine wave. this reduces the rms voltage applied to the lamp thus reducing the brightness. this is called natural dimming and the lytswitch lyt4311-4318 devices when confgured for dimming utilize natural dimming by reducing the led current as the rms line voltage decreases. by this nature, line regulation performance is purposely decreased to increase the dimming range and more closely mimic the operation of an incandescent lamp. using a 49.9 k w reference pin resistance selects natural dimming mode operation. leading edge phase controlled dimmers the requirement to provide ficker-free output dimming with low- cost, triac-based, leading edge phase dimmers introduces a number of trade-offs in the design. due to the much lower power consumed by led based lighting the current drawn by the overall lamp is below the holding current of the triac within the dimmer. this causes undesirable behaviors such as limited dimming range and/or fickering. the relatively large impedance the led lamp presents to the line allows signifcant ringing to occur due to the inrush current charging the input capacitance when the triac turns on. this too can cause similar undesirable behavior as the ringing may cause the triac current to fall to zero and turn off. to overcome these issues two circuits, the active damper and passive bleeder, are incorporated. the drawback of these circuits is increased dissipation and therefore reduced effciency of the supply so for non-dimming applications these components can simply be omitted. figure 10a shows the line voltage and current at the input of a leading edge triac dimmer with figure 10b showing the resultant rectifed bus voltage. in this example, the triac conducts at 90 degrees. 50 100 150 200 250 300 350 400 conduction angle () line voltage (at dimmer input) (v) line current (through dimmer) (a) 350 250 150 50 -50 -150 -250 -350 0.35 0.25 0.15 0.05 -0.05 -0.15 -0.25 -0.35 pi-5983-060810 voltage current 0.5 figure 10a. ideal input voltage and current waveform for a leading edge triac dimmer at 90 .
rev. b 02/13 10 lyt4211-4218/4311-4318 www.powerint.com 0 50 100 150 200 250 400 350 300 conduction angle () rectified input voltage (v) rectified input current (a) 350 300 250 200 150 100 50 0 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 pi-5984-060810 voltage current figure 10b. resultant waveforms following rectifcation of triac dimmer output . figure 12. ideal dimmer output voltage and current waveforms for a trailing edge dimmer at 90 conduction angle. figure 11. example of phase angle dimmer showing erratic firing. figure 11 shows undesired rectifed bus voltage and current with the triac turning off prematurely and restarting. if the triac is turning off before the end of the half-cycle erratically or alternate half ac cycles have different conduction angles then ficker will be observed in the led light due to variations in the output current. this can be solved by including a bleeder and damper circuit. dimmers will behave differently based on manufacturer and power rating, for example a 300 w dimmer requires less dampening and requires less power loss in the bleeder than a 600 w or 1000 w dimmer due to different drive circuits and triac holding current specifcations. multiple lamps in parallel driven from the same dimmer can introduce more ringing due to the increased capacitance of parallel units. therefore, when testing dimmer operation verify on a number of models, different line voltages and with both a single driver and multiple drivers in parallel. start by adding a bleeder circuit. add a 0.44 f capacitor and 510 w 1 w resistor (components in series) across the rectifed bus (c1 and r1 in figure 8). if the results in satisfactory operation reduce the capacitor value to the smallest that result in acceptable performance to reduce losses and increase effciency. if the bleeder circuit does not maintain conduction in the triac, then add an active damper as shown in figure 12. this consists of components r6, c3, and q1 in conjunction with r8. this circuit limits the inrush current that fows to charge c4 when the triac turns on by placing r8 in series for the frst 1 ms of the triac conduction. after approximately 1 ms, q1 turns on and shorts r8. this keeps the power dissipation on r8 low and allows a larger value to be used during current limiting. increasing the delay before q1 turns on by increasing the value of resistor r6 will improve dimmer compatibility but cause more power to be dissipated across r8. monitor the ac line current and voltage at the input of the power supply as you make the adjustments. increase the delay until the triac operates properly but keep the delay as short as possible for effciency. as a general rule the greater the power dissipated in the bleeder and damper circuits, the more types of dimmers will work with the driver. trailing edge phase controlled dimmers figure 11 shows the line voltage and current at the input of the power supply with a trailing edge dimmer. in this example, the dimmer conducts at 90 degrees. many of these dimmers use back-to-back connected power fets rather than a triac to control the load. this eliminates the holding current issue of triacs and since the conduction begins at the zero crossing, high current surges and line ringing are minimized. typically these types of dimmers do not require damping and bleeder circuits. 0 50 100 150 200 250 400 350 300 conduction angle () rectified input voltage (v) rectified input current (a) 350 300 250 200 150 100 50 0 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 pi-5985-060810 voltage current 50 100 150 200 250 300 350 conduction angle () dimmer output voltage (v) dimmer output current (a) 350 250 150 50 -50 -150 -250 -350 0.35 0.25 0.15 0.05 -0.05 -0.15 -0.25 -0.35 pi-5986-060810 voltage current 0
rev. b 02/13 11 lyt4211-4218/4311-4318 www.powerint.com audible noise considerations for use with leading edge dimmers noise created when dimming is typically created by the input capacitors, emi flter inductors and the transformer. the input capacitors and inductors experience high di/dt and dv/dt every ac half-cycle as the triac fres and an inrush current fows to charge the input capacitance. noise can be minimized by selecting flm vs. ceramic capacitors, minimizing the capacitor value and selecting inductors that are physically short and wide. the transformer may also create noise which can be minimized by avoiding cores with long narrow legs (high mechanical resonant frequency). for example, rm cores produce less audible noise than ee cores for the same fux density. reducing the core fux density will also reduce the noise. reducing the maximum fux density (bm) to 1500 gauss usually eliminates any audible noise but must be balanced with the increased core size needed for a given output power. thermal and lifetime considerations lighting applications present thermal challenges to the driver. in many cases the led load dissipation determines the working ambient temperature experienced by the drive so thermal evaluation should be performed with the driver inside the fnal enclosure. temperature has a direct impact on driver and led lifetime. for every 10 c rise in temperature, component life is reduced by a factor of 2. therefore it is important to properly heat sink and to verify the operating temperatures of all devices. layout considerations primary-side connections use a single point (kelvin) connection at the negative terminal of the input flter capacitor for the source pin and bias returns. this improves surge capabilities by returning surge currents from the bias winding directly to the input flter capacitor. the bypass pin capacitor should be located as close to the bypass pin and connected as close to the source pin as possible. the source pin trace should not be shared with the main power fet switching currents. all feedback pin components that connect to the source pin should follow the same rules as the bypass pin capacitor. it is critical that the main power fet switching currents return to the bulk capacitor with the shortest path as possible. long high current paths create excessive conducted and radiated noise. secondary-side connections the output rectifer and output flter capacitor should be as close as possible. the transformers output return pin should have a short trace to the return side of the output flter capacitor. figure 13. der-350 25 w layout example, top silk / bottom layer. pi-6904-101612 output capacitors voltage monitor pin resistor feedback pin resistor reference pin resistor input emi filter lyt4317eg bullk capacitor clamp transformer output diode output capacitor bypass pin capacitor
rev. b 02/13 12 lyt4211-4218/4311-4318 www.powerint.com quick design checklist maximum drain voltage verify that the peak v ds does not exceed 670 v under all operating conditions including start-up and fault conditions. maximum drain current measure the peak drain current under all operation conditions including start-up and fault conditions. look for signs of transformer saturation (usually occurs at highest operating ambient temperatures). verify that the peak current is less than the stated absolute maximum rating in the data sheet. thermal check at maximum output power, both minimum and maximum line voltage and ambient temperature; verify that temperature specifcations are not exceeded for the lytswitch, transformer, output diodes, output capacitors and drain clamp components.
rev. b 02/13 13 lyt4211-4218/4311-4318 www.powerint.com parameter symbol conditions source = 0 v; t j = -20 c to 125 c (unless otherwise specifed) min typ max units control functions switching frequency f osc t j = 65 c average 124 132 140 khz peak-peak jitter 5.4 frequency jitter modulation rate f m t j = 65 c see note b 2.6 khz bypass pin charge current i ch1 v bp = 0 v, t j = 65 c lyt4x11 -4.1 -3.4 -2.7 ma lyt4x12 -7.3 -6.1 -4.9 lyt4x13-4x17 -12 -9.5 -7.0 lyt4x18 -13.3 -10.8 -8.3 i ch2 v bp = 5 v, t j = 65 c lyt4x11 -0.81 -0.62 -0.43 lyt4x12 -3.1 -2.4 -1.7 lyt4x13-4x17 -5.6 -4.35 -3.1 lyt4x18 -6.75 -5.5 -4.25 charging current temperature drift see note a, b 0.7 %/c bypass pin voltage v bp 0 c < t j < 100 c 5.75 5.95 6.15 v bypass pin voltage hysteresis v bp(h) 0 c < t j < 100 c 0.85 v bypass pin shunt voltage v bp(shunt) i bp = 4 ma 0 c < t j < 100 c 6.1 6.4 6.6 v soft-start time t soft t j = 65 c v bp = 5.9 v 55 76 ms absolute maximum ratings (1,4) drain pin peak current (5) : ly t4x11 ................................. 1.37 a ly t4x12 ................................ 2.08 a ly t4x13 ................................. 2.72 a ly t4x14 ................................ 4.08 a ly t4x15 ................................ 5.44 a ly t4x16 ................................ 6.88 a ly t4x17 ................................. 7.73 a ly t4x18 ................................ 9.00 a drain pin voltage ................ -0.3 to 670 v bypass pin voltage ................................................. -0.3 to 9 v bypass pin current ..................... 100 ma voltage monitor pin voltage ............................... -0.3 to 9 v feedback pin voltage .. .................................. -0.3 to 9 v reference pin voltage .......................................... -0.3 to 9 v lead temperature (3) ........................................................ 260 c storage temperature . .................. -65 to 150 c operating junction temperature (2) ........................ -40 to 150 c notes: 1. all voltages referenced to source, t a = 65 c. 2. normally limited by internal circuitry. 3. 1/16 in. from case for 5 seconds. 4. absolute maximum ratings specifed may be applied, one at a time without causing permanent damage to the product. exposure to absolute maximum ratings for extended periods of time may affect product reliability. 5. peak drain current is allowed while the drain voltage is simultaneously less than 400 v. see also figure 13. thermal resistance thermal resistance: e or l package ( q ja ) .......................... .......................... 105 c/w (1) ( q jc ) .................................................... 2 c/w (2) notes: 1. free standing with no heat sink. 2. measured at back surface tab.
rev. b 02/13 14 lyt4211-4218/4311-4318 www.powerint.com parameter symbol conditions source = 0 v; t j = -20 c to 125 c (unless otherwise specifed) min typ max units control functions (cont.) drain supply current i cd2 0 c < t j < 100 c fet not switching 0.5 0.8 1.2 ma i cd1 0 c < t j < 100 c fet switching at f osc 1 2.5 4 voltage monitor pin line overvoltage threshold i ov t j = 65 c r r = 24.9 k w r r = 49.9 k w threshold 115 123 131 a hysteresis 6 voltage monitor pin voltage v v 0 c < t j < 100 c i v < i ov 2.75 3.0 3.25 v voltage monitor pin short-circuit current i v(sc) v v = 5 v t j = 65 c 165 185 205 a remote on/off threshold v v(rem) t j = 65 c 0.5 v feedback pin feedback pin current at onset of maximum duty cycle i fb(dcmaxr) 0 c < t j < 100 c 90 a feedback pin current skip cycle threshold i fb(skip) 0 c < t j < 100 c 220 a maximum duty cycle dc max i fb(dcmaxr) < i fb < i fb(skip) 0 c < t j < 100 c 90 99.9 % feedback pin voltage v fb i fb = 150 a 0 c < t j < 100 c 2.1 2.3 2.56 v feedback pin short-circuit current i fb(sc) v fb = 5 v t j = 65 c 320 400 480 a duty cycle reduction dc10 i fb = i fb(ar) , t j = 65 c, see note b 17 % dc40 i fb = 40 a, t j = 65 c 34 dc60 i fb = 60 a, t j = 65 c 55 auto-restart auto-restart on-time t ar t j = 65 c v bp = 5.9 v 55 76 ms auto-restart duty cycle dc ar t j = 65 c see note b 25 % soa minimum switch on-time t on(soa) t j = 65 c see note b 1.75 s feedback pin current during auto-restart i fb(ar) 0 c < t j < 100 c 6.5 10 a
rev. b 02/13 15 lyt4211-4218/4311-4318 www.powerint.com parameter symbol conditions source = 0 v; t j = -20 c to 125 c (unless otherwise specifed) min typ max units reference pin reference pin voltage v r r r = 24.9 k w 0 c < t j < 100 c 1.223 1.245 1.273 v reference pin current i r 48.69 49.94 51.19 a current limit/circuit protection full power current limit (c bp = 4.7 f) i limit(f) t j = 65 c di/dt = 174 ma/ s lyt4x12 1.00 1.17 a di/dt = 174 ma/ s lyt4x13 1.24 1.44 di/dt = 225 ma/ s lyt4x14 1.46 1.70 di/dt = 320 ma/ s lyt4x15 1.76 2.04 di/dt = 350 ma/ s lyt4x16 2.43 2.83 di/dt = 426 ma/ s lyt4x17 3.26 3.79 reduced power current limit ( c bp = 47 f) i limit(r) t j = 65 c di/dt = 133 ma/ s lyt4x11 0.74 0.86 a di/dt = 195 ma/ s lyt4x12 0.81 0.95 di/dt = 192 ma/ s lyt4x13 1.00 1.16 di/dt = 240 ma/ s lyt4x14 1.19 1.38 di/dt = 335 ma/ s lyt4x15 1.43 1.66 di/dt = 380 ma/ s lyt4x16 1.76 2.05 di/dt = 483 ma/ s lyt4x17 2.35 2.73 di/dt = 930 ma/ s lyt4x18 4.90 5.70 minimum on-time pulse t leb + t il(d) t j = 65 c 300 500 700 ns leading edge blanking time t leb t j = 65 c see note b 150 500 ns current limit delay t il(d) t j = 65 c see note b 150 ns thermal shutdown temperature see note b 135 142 150 c thermal shutdown hysteresis see note b 75 c bypass pin power-up reset threshold voltage v bp(reset) 0 c < t j < 100 c 2.25 3.30 4.25 v
rev. b 02/13 16 lyt4211-4218/4311-4318 www.powerint.com parameter symbol conditions source = 0 v; t j = -20 c to 125 c (unless otherwise specifed) min typ max units output on-state resistance r ds(on) lyt4x11 i d = 100 ma t j = 65 c 11.5 13.2 w t j = 100 c 13.5 15.5 lyt4x12 i d = 100 ma t j = 65 c 6.9 8.0 t j = 100 c 8.4 9.7 lyt4x13 i d = 150 ma t j = 65 c 5.3 6.0 t j = 100 c 6.3 7.3 lyt4x14 i d = 150 ma t j = 65 c 3.4 3.9 t j = 100 c 3.9 4.5 lyt4x15 i d = 200 ma t j = 65 c 2.5 2.9 t j = 100 c 3.0 3.4 lyt4x16 i d = 250 ma t j = 65 c 1.9 2.2 t j = 100 c 2.3 2.7 lyt4x17 i d = 350 ma t j = 65 c 1.7 2.0 t j = 100 c 2.0 2.4 lyt4x18 i d = 600 ma t j = 65 c 1.3 1.5 t j = 100 c 1.6 1.8 off-state drain leakage current i dss v bp = 6.4 v v ds = 560 v t j = 100 c 50 a breakdown voltage bv dss v bp = 6.4 v t j = 65 c 670 v minimum drain supply voltage t j < 100 c 36 v rise time t r measured in a typical flyback see note b 100 ns fall time t f 50 ns notes: a. for specifcations with negative values, a negative temperature coeffcient corresponds to an increase in magnitude with increasing temperature and a positive temperature coeffcient corresponds to a decrease in magnitude with increasing temperature. b. guaranteed by characterization. not tested in production.
rev. b 02/13 17 lyt4211-4218/4311-4318 www.powerint.com typical performance characteristics figure 14. drain capacitance vs. drain pin voltage. figure 15. power vs. drain voltage. figure 16. drain current vs. drain voltage. figure 17. maximum allowable drain current vs. drain voltage. 0 100 200 300 400 500 600 0 100 1000 10000 pi-6715-071012 drain pin voltage (v) drain capacitance (pf) lyt4x11 0.18 lyt4x12 0.28 lyt4x13 0.38 lyt4x14 0.56 lyt4x15 0.75 lyt4x16 1.00 lyt4x17 1.16 lyt4x18 1.55 scaling factors: 300 100 200 0 0 200 100 400 500 600 300 700 drain voltage (v) power (mw) pi-6716-071012 lyt4x11 0.18 lyt4x12 0.28 lyt4x13 0.38 lyt4x14 0.56 lyt4x15 0.75 lyt4x16 1.00 lyt4x17 1.16 lyt4x18 1.55 scaling factors: 0 0 2 4 6 8 10 12 14 16 18 20 drain voltage (v) drain current (a) pi-6717-071012 2 3 1 lyt4x28 t case = 25 c lyt4x28 t case = 100 c 4 5 lyt4x11 0.18 lyt4x12 0.28 lyt4x13 0.38 lyt4x14 0.56 lyt4x15 0.75 lyt4x16 1.00 lyt4x17 1.16 lyt4x18 1.55 scaling factors: 0 0 100 200 300 400 600 500 700 800 drain voltage (v) drain current (normalized to absolute maximum rating) pi-6909-110512 0.6 0.8 0.4 0.2 1 1.2
rev. b 02/13 18 lyt4211-4218/4311-4318 www.powerint.com pi-4917-061510 mounting hole pattern (not to scale) pin 7 pin 1 0.100 (2.54) 0.100 (2.54) 0.059 (1.50) 0.059 (1.50) 0.050 (1.27) 0.050 (1.27) 0.100 (2.54) 0.155 (3.93) 0.020 (0.50) notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. maximum mold protrusion is 0.007 [0.18] per side. 3. dimensions noted are inclusive of plating thickness. 4. does not include inter-lead flash or protrusions. 5. controlling dimensions in inches (mm). 0.403 (10.24) 0.397 (10.08) 0.325 (8.25) 0.320 (8.13) 0.050 (1.27) front view 2 2 b a 0.070 (1.78) ref. pin #1 i.d. 3 c 0.016 (0.41) ref. 0.290 (7.37) ref. 0.047 (1.19) 0.100 (2.54) 0.519 (13.18) ref. 0.198 (5.04) ref. 0.264 (6.70) ref. 0.118 (3.00) 6 6 3 0.140 (3.56) 0.120 (3.05) 0.021 (0.53) 0.019 (0.48) 0.378 (9.60) ref. 0.019 (0.48) ref. 0.060 (1.52) ref. 0.048 (1.22) 0.046 (1.17) 0.081 (2.06) 0.077 (1.96) 0.207 (5.26) 0.187 (4.75) 0.033 (0.84) 0.028 (0.71) 0.016 (0.41) 0.011 (0.28) esip-7c (e package) 10 ref. all around 0.020 m 0.51 m c 0.010 m 0.25 m c a b side view end view back view 4 0.023 (0.58) 0.027 (0.70) detail a detail a
rev. b 02/13 19 lyt4211-4218/4311-4318 www.powerint.com part ordering information ? lytswitch product family ? 4 series number ? pfc/dimming 2 pfc no dimming 3 pfc dimming ? voltage range 1 low-line ? device size ? package identifer e esip-7c l esip-7f lyt 4 2 1 3 e 1 7 end view 0.021 (0.53) 0.019 (0.48) 0.060 (1.52) ref. 0.019 (0.48) ref. 0.378 (9.60) ref. 0.048 (1.22) 0.046 (1.17) c side view 6 0.129 (3.28) 0.122 (3.08) 0.081 (2.06) 0.077 (1.96) detail a 0.084 (2.14) 0.047 (1.19) ref. 0.290 (7.37) ref. 0.016 (0.41) 0.011 (0.28) 0.020 m 0.51 m c 3 pi-5204-061510 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. maximum mold protrusion is 0.007 [0.18] per side. 3. dimensions noted are inclusive of plating thickness. 4. does not include inter-lead flash or protrusions. 5. controlling dimensions in inches (mm). esip-7f (l package) 2 a b 1 7 bottom view pin 1 i.d. 0.403 (10.24) 0.397 (10.08) 0.325 (8.25) 0.320 (8.13) 0.050 (1.27) 0.070 (1.78) ref. exposed pad hidden exposed pad up 2 1 7 top view 0.089 (2.26) 0.079 (2.01) 0.173 (4.40) 0.163 (4.15) 0.198 (5.04) ref. 0.264 (6.70) ref. 0.100 (2.54) 0.490 (12.45) ref. 6 0.033 (0.84) 0.028 (0.71) 0.010 m 0.25 m c a b 4 3 0.020 (0.50) 0.023 (0.58) 0.027 (0.70) detail a (not drawn to scale)
for the latest updates, visit our website: www.powerint.com power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. power integrations does not assume any liability arising from the use of any device or circuit described herein. power integrations makes no warranty herein and specifically disclaims all warranties including, without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement of third party rights. patent information the products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more u.s. and foreign patents, or potentially by pending u.s. and foreign patent applications assigned to power integrations. a complete list of power integrations patents may be found at www.powerint.com. power integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. life support policy power integrations products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of power integrations. as used herein: 1. a life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signifcant injury or death to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. the pi logo, topswitch, tinyswitch, linkswitch, lytswitch, dpa-switch, peakswitch, capzero, senzero, linkzero, hiperpfs, hipertfs, hiperlcs, qspeed, ecosmart, clampless, e-shield, filterfuse, stakfet, pi expert and pi facts are trademarks of power integrations, inc. other trademarks are property of their respective companies. ?2013, power integrations, inc. power integrations worldwide sales support locations world headquarters 5245 hellyer avenue san jose, ca 95138, usa. main: +1-408-414-9200 customer service: phone: +1-408-414-9665 fax: +1-408-414-9765 e-mail: usasales@powerint.com china (shanghai) rm 1601/1610, tower 1, kerry everbright city no. 218 tianmu road west, shanghai, p.r.c. 200070 phone: +86-21-6354-6323 fax: +86-21-6354-6325 e-mail: chinasales@powerint.com china (shenzhen) 3rd floor, block a, zhongtou international business center, no. 1061, xiang mei rd, futian district, shenzhen, china, 518040 phone: +86-755-8379-3243 fax: +86-755-8379-5828 e-mail: chinasales@powerint.com germany lindwurmstrasse 114 80337 munich germany phone: +49-895-527-39110 fax: +49-895-527-39200 e-mail: eurosales@powerint.com india #1, 14th main road vasanthanagar bangalore-560052 india phone: +91-80-4113-8020 fax: +91-80-4113-8023 e-mail: indiasales@powerint.com italy via milanese 20, 3rd. fl. 20099 sesto san giovanni (mi) italy phone: +39-024-550-8701 fax: +39-028-928-6009 e-mail: eurosales@powerint.com japan kosei dai-3 bldg. 2-12-11, shin-yokohama, kohoku-ku yokohama-shi kanagwan 222-0033 japan phone: +81-45-471-1021 fax: +81-45-471-3717 e-mail: japansales@powerint.com korea rm 602, 6fl korea city air terminal b/d, 159-6 samsung-dong, kangnam-gu, seoul, 135-728, korea phone: +82-2-2016-6610 fax: +82-2-2016-6630 e-mail: koreasales@powerint.com singapore 51 newton road #19-01/05 goldhill plaza singapore, 308900 phone: +65-6358-2160 fax: +65-6358-2015 e-mail: singaporesales@powerint.com taiwan 5f, no. 318, nei hu rd., sec. 1 nei hu dist. taipei 11493, taiwan r.o.c. phone: +886-2-2659-4570 fax: +886-2-2659-4550 e-mail: taiwansales@powerint.com europe hq 1st floor, st. jamess house east street, farnham surrey gu9 7tj united kingdom phone: +44 (0) 1252-730-141 fax: +44 (0) 1252-727-689 e-mail: eurosales@powerint.com applications hotline world wide +1-408-414-9660 applications fax world wide +1-408-414-9760 revision notes date a initial release. 11/12 b corrected min and typ parameter table values on pages 13 and 14. 02/13 b updated parameters i ch1 , i ch2 , i cd1 , dc ar , i limit(f) , i limit(r) , on pages 13, 14 and 15. 02/20/13

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